As technology improves with time, some design techniques such as ECL and CML, once set aside, are now reconsidered. Due to that technological evolution, device area has decreased significantly and dynamic power dissipation has been reduced with the size of transistors. For example, a paper by H. -M. Rein et al. entitled "Design Considerations for Very-High-Speed Si-Bipolar IC's Operating Up to 50 Gb/s", IEEE Journal of Solid-State Circuits, Vol. 31, No. 8, pp. 1076-1089, August 1996, reports circuits which lead to gate delays far below 1 ns and bit rates of up to 50 Gb/s. ECL/CML bipolar technologies have an edge over CMOS when speed is the main concern. For example, architectures of Gb/s transceivers described by R. X. Gu et al., "High Performance Digital VLSI Circuit Design", Kluwer Academic Publishers, Boston, 312 pages, Chapters 6 and 8,1996, are implemented in two level CML and ECL circuits.
Considering the growing popularity of CML circuits, their testability should be assessed carefully. A quick look at the literature shows that ECL/CML testability has not been thoroughly studied. It appears that due to their market dominance, MOS technologies have attracted most of the attention of the industrial and scientific community. However, some recent works on ECL/CML testability have shown that these circuits have unique fault sensitivities, and that testability of classical stuck-at faults is far from providing sufficient defect coverage. See M. O. Esonu et al., "Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits", VLSI Design, Vol. 1, No. 4, pp 261-276,1994; S. M. Menon, Y. K. Malaiya et al., "Fault Modeling of ECL for High Fault Coverage of Physical Defects", VLSI Design, Vol. 4, No. 3, pp. 231-242,1996; F. Anderson, "Emitter Coupled Logic and Cascode Current Switch Testability and Design for Test", IEEE Southern Technical Conference, pp. 119-126, October 1988; and U. Jorczyk, W. Daehn and O. Neumann, "Fault Modeling of Differential ECL", EURODAC 1995, pp. 190-195, April 1995.
Furthermore, it is shown that ECL combinational gate chains have a tendency to heal back from faults in the first stages (see F. Anderson publication). Frequently reported faults are line stuck-at faults, truth-table faults, like, wired-OR, byzantine, reduced noise-margin, undefined logic-level, delay, feedback oscillation, sequential behaviour and quiescent current I.sub.ddq.
For example, the "line stuck-at" faults are described by Esonu et al. 1994 publication and C. Morandi et al., "ECL Fault Modelling", IEE Proceedings, Vol. 135, Pt. E, No. 6, pp. 312-317, November 1988. The "truth-table" faults are described by Esonu et al. 1994 publication. The "like" is described by S. M. Menon, Y. K. Malaiya, and A. P. Jayasumana 1996 publication. The "wired-OR" is described by S. M. Menon, A. P. Jayasumana, Y. K. Malaiya, and D. R. Clinkinbeard, "Modelling and Analysis of Bridging Faults in Emitter-Coupled Logic (ECL) Circuits", IEE Proceedings-E, Vol. 140, No. 4, pp. 220-226, July 1993. The "byzantine" faults are described by F. Anderson 1988 publication. The "reduced noise-margin" is described by Esonu et al 1994 publication; and F. Anderson 1988 publication. The "undefined logic-level" is described by U. Jorczyk, W. Daehn and O. Neumann 1995 publication and S. M. Menon, A. P. Jayasumana, Y. K. Malaiya, D. R. Clinkinbeard 1993 publication. The "delay" faults are described by Esonu et al. 1994 publication and U. Jorczyk, W. Daehn and O. Neumann 1995 publication. The "feedback oscillation" faults are described by S. M. Menon, A. P. Jayasumana, Y. K. Malaiya, D. R. Clinkinbeard 1993 publication. The "sequential behaviour" faults are described by S. M. Menon, A. P. Jayasumana, Y. K. Malaiya, D. R. Clinkinbeard 1993 publication. The "quiescent current I.sub.ddq " faults are described by Esonu et al. 1994 publication.
The probable manufacturing defects causing these faults are inter-connect and resistor shorts or opens, piped transistors, bridges (wires making contact) and broken lines (see Esonu et al. 1994, Menon/Malaiya/Jayasumana 1996, and Jorczyk/Daehn/Neumann 1995).
To deal with the observed variety of faults, design for testability methods of several flavours were proposed. For instance, a simple technique to test for like-faults in ECL was devised by Menon (see Menon/Malaiya/Jayasumana 1996). The proposed technique uses a standard XOR gate to verify the complementary behaviour of the gate outputs. This technique introduces a very high area overhead (one test gate for every circuit gate), and it deals only with a very specific and not so frequent fault. Delay measurement techniques have been developed to test ECL-CMOS RAM macros (see K. Higeta et al., "A Soft Error-Immune 0.9 ns 1.15 Mb ECL-CMOS SRAM with 30 ps 120 k Logic Gates and Onchip Test Circuitry", IEEE 1995 Bipolar Circuits and Technology Meeting, pp. 47-50, 1995). Using ECL flip-flops on the inputs and outputs of the CMOS RAM macros and using a pattern generator to stimulate the memories, Higeta et al. measured the path delay within the macros in test clock cycles. This technique may be useful for CML circuits, however it cannot fully test for even obvious delay faults. Considering that each gate can have a modest variation in delay of 10% of nominal value, a tester evaluating a 10 gate deep chain could escape a faulty gate going twice slower than nominal, when all others have their nominal delay value. Also, an at-speed built-in self-test (BIST) circuit was proposed by Jorczyk et al. (see U. Jorczyk, W. Daehn, "Built-in self-test for high speed integrated circuits", SPIE, Vol. 2874, pp. 162-172, 1996) to test ECL integrated circuits, and it is shown that it yields a better defect detection than slow speed test. However, this technique requires significant design efforts and high area overhead.
To deal with the problem of reduced noise-margins and of fault symptoms healing, Anderson presents a technique that would stress a circuit enough to make the recovery impossible, forcing the fault to appear as stuck-at (see Anderson publication and U.S. Pat. No. 4,604,531 granted to Gersbach et al on Aug. 5, 1986). This technique uses two additional power lines in test mode to bias the differential stage of all gates one way or the other. Small devices are added to each gate to isolate the circuit from the additional lines in normal mode and to protect the circuit from unwanted noise and loading. U.S. Pat. No. 4,902,916 entitled "Identification of defects in emitter-coupled logic circuits" granted to Cecchi et al. on Feb. 20, 1990 discloses another technique oriented toward a specific fault that could not be observed easily. The cause of the fault had been pinpointed to a probable defect related to the contact layer. Through modification of the layout of standard cells, they are able to guarantee that any defect within this layer could only map into a stuck-at fault.